1. Field of the Invention
The field of the invention is data processing, or, more specifically, leakage tolerant phase locked loop (PLL) circuit devices and methods of locking a phase of a feedback signal to a phase of a reference signal using a leakage tolerant phase locked loop (PLL) circuit device.
2. Description of Related Art
A phase locked loop (PLL) circuit device is a control system that generates an output signal whose phase is locked relative to a phase of an input reference signal. With frequency being a derivative of phase, the output signal's frequency is hence locked relative to frequency of input reference signal. Consequently, a PLL can track an input frequency, or can generate a frequency that is a multiple of input frequency used for indirect frequency synthesis. For further explanation, FIG. 1 sets forth a diagram of a PLL circuit device found in the prior art. In the PLL circuit device of FIG. 1, the phase difference between a reference signal (118) and a feedback signal (128) is translated by a phase detector (102) into two signals, increase frequency signal (120) and decrease frequency signal (122). The two signals (120, 122) control a charge pump (104) that steers current into or out of a filter capacitor (106) via a filter control signal (124), causing the voltage across the filter capacitor (106) to increase or decrease. In each cycle, the time during which the charge pump (104) is turned-on is proportional to the phase difference between the reference signal (118) and the feedback signal (128). Hence, the charge delivered by the charge pump (104) is also dependent on the phase difference. The voltage on the filter capacitor (106) is used to control a voltage controlled oscillator (VCO) (108), which increases or decreases the frequency of a VCO output signal (130). The VCO outputs (130) may have a frequency that is larger than the frequency of the reference signal (118) and as such, a feedback divider (190) may be used to generate the feedback signal (128) to compare with the reference signal (118). Thus, increasing or decreasing the frequency of the VCO output signal (130) also increases or decreases the frequency of the feedback signal (128). That is, the filter capacitor (106) is instrumental in controlling how efficiently the VCO (108) and the PLL circuit device, as a whole, is able to lock the phase of the feedback signal (128) to the phase of the reference signal (118).
In an effort to control costs or reduce the size of the components with PLL circuit devices, manufacturers may select a filter capacitor with poor leakage characteristics. A leaky filter capacitor may discharge some of its charge during the operation of the PLL circuit device. Because a PLL circuit device relies on the charge of its filter capacitor to indicate to a VCO an amount to increase or decrease frequencies of the VCO output signal, a leaky filter capacitor may cause the VCO to not adjust the frequency of the VCO output signal as indicated by the phase difference determined by the phase detector. That is, a leaky filter capacitor could increase the number of frequency cycles that the PLL circuit device must operate to lock the phase of the feedback signal to a phase of a reference signal. In some instances, the degree of leakage in the filter capacitor may prevent a PLL circuit device from completely phase locking the feedback signal to the reference signal.
For further explanation, FIG. 2 sets forth a diagram illustrating a transient response of the PLL circuit device of FIG. 1, configured with a leaky filter capacitor. As explained above, the goal of a PLL circuit device is to lock a phase of a feedback signal to a phase of a reference signal.
The transient response of FIG. 2 illustrates the reference signal (118) and the feedback signal (128) at multiple time points (250-257) over time (290). At the time point (250), there is a phase difference between the two signals (118, 128). That is, the rising edge of the reference signal (118) begins at the time point (250) and the next rising edge of the feedback signal (128) begins at the time point (251). In response to detecting this difference between the two signals (118, 128), the phase detector (102) generates the increase frequency signal (120) during the two time points (250, 251) and the charge pump provides a corresponding charge to the filter capacitor (106). During the time points (250, 251), the VCO control signal (126) is generated that corresponds to the charge of the filter capacitor (106). However, between the time point (251) and the time point (252), the increase frequency error signal (120) is not generated and the charge pump (104) does not continue to charge the filter capacitor (106). In the examples of FIGS. 1-2, the reference plate of the filter capacitor (106) is coupled to a low potential or ground, hence leakage in the filter capacitor (106) occurs in that direction. Because the filter capacitor (106) is leaky, the filter capacitor (106) begins to discharge and thus the VCO control signal (126) begins to decrease. In fact, at the time point (252), the filter capacitor (106) is at substantially the same charge it was at before the time point (250). As a consequence of the filter capacitor (106) discharging, the frequency of the feedback signal (128) is not increased and the same increase frequency signal (120) is generated between time points (252-257). That is, the leakage in the filter capacitor (106) prevents the PLL circuit device of FIG. 1 from locking the phase of the feedback signal (128) to a phase of the reference signal (118). Hence, preventing the VCO output signal (130) from reaching and settling at a target frequency. This also causes wide frequency variations during each reference signal cycle, translating to wide jitter of the VCO output signal (130).